1. Field of the Invention
The present invention relates to a resin sealed semiconductor integrated circuit device which is obtained by sealing a semiconductor chip with resin.
2. Description of Related Art
The semiconductor chip is constructed by a plurality of electronic elements formed on a semiconductor substrate such as silicon substrate and wirings such as aluminum wirings which connect these electronic elements. These wirings are formed on the semiconductor substrate in two or more layers via intermediate insulating films of silicon dioxide or the like. Further, the surface of the semiconductor chip is coated with a nitride film or the like in order to protect the surface. Then, a resin sealing is provided to protect the semiconductor chip from damages caused by external forces or an ambient environment.
On the other hand, due to the difference in the coefficients of thermal expansion between silicon that constitutes the semiconductor chip and the resin that is the sealing material the semiconductor chip is subjected to a thermal stress during the operation of the semiconductor integrated circuit device or at the time of giving resin sealing, which may lead to a damage to the semiconductor integrated circuit device. In addition, because of the thermal stress, cracks are often generated in the protective film or the intermediate insulating films of the semiconductor chip, which may cause nonfunctioning of the semiconductor integrated circuit device.
Ordinarily, an aluminum material with high malleability and ductility is employed for the wirings of semiconductor integrated circuit devices, and for the sealing resin, an epoxy resin containing silica or the like is used. For example, when the temperature of the device is raised to 200.degree. C. at the time of resin sealing and then cooled down to a normal temperature, the contraction stress of the sealing resin is applied as it is to be semiconductor chip. The contraction stress points along the surface of the semiconductor chip in the direction from the periphery toward the center of the semiconductor chip, so that especially at and near the corner portions of the semiconductor chip where the upper wiring and the lower wiring intersect perpendicularly with each other a maximum contraction stress acts in the direction toward the chip center bisecting the right angle formed by the intersecting wirings. Under the action of the contraction stress, the semiconductor substrate, the lower wiring, the intermediate insulating film, the upper wiring and the protective film are respectively deformed in the direction of the stress. However, the component with the largest amount of the deformation is the protective film in the uppermost layer, the amount of deformation decreasing as one moves downward, with less amount of deformation for the semiconductor substrate and the lower wiring.
Therefore, in the intersecting portions where the upper wiring overlaps with the lower wiring, the upper wiring and the protective film are shifted substantially toward the center of the semiconductor chip. The largest amount of shift may reach 3 to 5 .mu.m for a semiconductor chip of 7 mm square. On the other hand, in the portion where the upper wiring and the lower wiring do not overlap, the degree of adhesion between the intermediate insulating film and the protective film is high due to their direct contact, and the degree of adhesion between the semiconductor substrate and the intermediate insulating film is also high, so that the amount of shift of the intermediate insulating film and the protective film is small being 1 to 2.mu.m. As seen in the above, in the step part in the vicinity of the boundary where the upper wiring and the lower wiring intersect perpendicularly with each other, a deviation is generated due to the difference in the amounts of shift along the direction perpendicular to the protective film, so that there can be generated cracks not only in the protective film but also to the intermediate insulating film.
Japanese patent Laid Open No. 57-45259 discloses such a technique that holes or slits are formed within a guardband wiring layer to reduce crack failure produced in a passivation layer which is formed on the wiring layer. However, the prior art countermeasure is not effective to a multi-wiring layer structure.